1 Introduction. - 1. 1 Aims. - 1. 2 Background. - 1. 3 Synopsis. - 2 Design Motivations. - 2. 1 Introduction. - 2. 2 Software motivations. - 2. 3 Hardware motivations. - 2. 4 Summary of hardware and software requirements. - 3 Current Processor Models. - 3. 1 Introduction. - 3. 2 Control-flow processors. - 3. 3 Data-flow processors. - 3. 4 Summary. - 4 Introduction to Multithreaded Processors. - 4. 1 Introduction. - 4. 2 Multiple contexts. - 4. 3 Communication. - 4. 4 Synchronisation and scheduling. - 4. 5 Memory. - 4. 6 Microthread size. - 4. 7 Summary. - 5 Hardware Scheduling. - 5. 1 Introduction. - 5. 2 Background. - 5. 3 The tagged up/down sorter. - 5. 4 Clocked digital implementations. - 5. 5 Conclusions. - 6 Memory Structure. - 6. 1 Introduction. - 6. 2 Memory performance. - 6. 3 Memory hierarchy for control-flow processors. - 6. 4 Maintaining memory access frequency. - 6. 5 Virtual addressing for the memory tree. - 6. 6 Scalable memory protection. - 6. 7 Tree routers. - 6. 8 Summary. - 7 Anaconda A Multithreaded Processor. - 7. 1 Introduction. - 7. 2 Data driven microthreads. - 7. 3 Matching. - 7. 4 Scheduling. - 7. 5 Memory structure. - 7. 6 Exceptions and types. - 7. 7 Instructions. - 7. 8 Cache control and preloading context. - 7. 9 Nanokernel support. - 7. 10 Input output and timers. - 7. 11 Execution unit pipeline. - 7. 12 Summary. - 8 Evaluation. - 8. 1 Introduction. - 8. 2 Assembler. - 8. 3 Simulator. - 8. 4 Memory copy test. - 8. 5 Livermore loop 7 test. - 8. 6 Signalling and mutual exclusion. - 8. 7 Interdomain remote procedure calls. - 8. 8 Conclusions. - 9 Conclusions. - 9. 1 Review. - 9. 2 Future Research. - References. - A Anaconda Instruction Formats. - B Anaconda Memory Copy Program. Language: English